Silicon carbide (that will be referred to as SiC) has a wide band gap, and its maximum breakdown electric field is larger than that of silicon (that will be referred to as Si) by one order of magnitude. Thus, SiC has been considered as a material advantageously used for power semiconductor devices in the next generation. Such devices as Shottky diodes, vertical MOSFETs, and thyristors, using SiC as a semiconductor material have been proposed, and it has been confirmed that these devices exhibit far more excellent characteristics than known devices using Si. The present invention is particularly concerned with a SiC vertical MOSFET, among the above-indicated devices.
FIG. 7 is a cross sectional view of a unit cell of a planar type vertical MOSFET, which is the most prevailing type of power semiconductor device using Si. When a voltage is applied to a gate electrode layer 6 on a gate insulating film 5, a channel 10 is induced in a surface portion of a p base region 3 right under the gate electrode layer 6, and an n source region 4 and an n drift layer 2 are electrically shorted. As a result, current is allowed to flow from a drain electrode 8 formed on the rear surface of an n.sup.+ substrate 1 under the n drift layer 2, to a source electrode 7 formed on the surface of the n source region 4. When the voltage applied to the gate electrode layer 6 is removed, the drain electrode 8 and source electrode 7 are electrically disconnected from each other. Thus, the vertical MOSFET of FIG. 7 performs a switching function by applying and removing voltage to and from the gate electrode layer 6.
FIG. 9(a) through FIG. 9(f) are cross sectional views showing the flow of the process of fabricating the structure as described above. The process shown in these figures is only a part of the whole process of producing the semiconductor device, in particular, a process of forming junctions that relates to the present invention.
Initially, the n drift layer 2 having high resistance is epitaxially grown on the n.sup.+ substrate 1, and the gate insulating film 5 in the form of a silicon dioxide film (referred to as "SiO.sub.2 film") is formed by thermal oxidation on the surface of the n drift layer 2. Then, a polycrystalline silicon layer 6a is deposited on the gate insulating film 5, as shown in FIG. 9(a). The polycrystalline silicon layer 6a is then formed in a given pattern by photolithography to provide the gate electrode layer 6, as shown in FIG. 9(b).
Subsequently, p-type impurities, such as boron ions 3a, are implanted, as shown in FIG. 9(c), and the implanted boron atoms 3b are activated and diffused by heat treatment to form the p base region 3, as shown in FIG. 9(d).
Further, n-type impurities, such as phosphorous ions 4a, are implanted, as shown in FIG. 9(e), and the implanted phosphorous atoms 4b are activated and diffused by heat treatment to form the n source region 4, as shown in FIG. 9(f).
In the following steps that are not illustrated, phosphorous glass is deposited by reduced-pressure chemical vapor deposition (CVD) to provide an insulating film, and an opening or window is formed through the insulating film, so that the source electrode 7 is formed in contact with the n source region 4. At the same time, a gate electrode is formed in contact with the gate electrode layer 6, and a drain electrode is provided on the rear surface of the n.sup.+ substrate 1.
What is most important in the above-described process is as follows: in the process of implanting the p-type boron ions 3a and n-type phosphorous ions 4a, the gate electrode layer 6 formed in the previous step serves as a mask during ion implantation, and both types of ions are introduced into the n drift layer 2 using the same mask, and then thermally diffused. The thus formed structure is called double diffusion MOS (D-MOS) structure. In this manner, the length of the channel region 10 that greatly influences characteristics of the MOSFET can be controlled with considerably high accuracy, thus assuring a high yield in the manufacture of the MOSFET.
The above-described process has been most widely employed to produce MOSFETs using Si as a semiconductor material, but cannot applied as it is when producing MOSFETs using SiC. This is because SiC has poor ability to activate impurities introduced by ion implantation, and, in order to improve this ability, ion implantation at 1000.degree. C. or higher and heat treatment for activation at 1600.degree. C. or higher are needed. In addition, the impurities introduced by ion implantation hardly diffuses in the SiC substrate.
While SiO.sub.2 film is normally used as a gate insulating film, and polycrystalline silicon is used as a gate electrode, the SiO.sub.2 film softens at 1300.degree. C. or higher, and polycrystalline silicon has a fusing point of 1412.degree. C. Accordingly, heat treatment cannot be implemented at such high temperatures as indicated above after the gate insulating film 5 and gate electrode layer 6 are formed, as in the process of FIG. 9(a) through FIG. 9(f).
In view of the above problem, trench-type MOSFETs have been proposed which use SiC substrates. FIG. 10 is a cross sectional view showing a unit cell of a known example of trench-type MOSFETs.
In the structure shown in FIG. 10, a p base layer 13 is formed by epitaxial growth, rather than by diffusing impurities. After an n source region 14 is formed by implantation of phosphorous ions, for example, a trench 19 is formed which extends from the surface of the n source region 14 down to n drift layer 12. Gate insulating film 15 is formed on the inner wall of the trench 19, and a gate electrode layer 16 is formed to fill the interior of the trench 19. The thus formed structure may be also advantageously employed as a Si device. This is because channel regions 20 are formed in the vertical direction in this structure, thus allowing cells to be closely positioned with high area efficiency, and the resulting device exhibits improved characteristics due to its geometry.
When the above structure is employed in SiC devices, however, there arises another problem as follows. The boundary condition of the electric field strength at the interface between the semiconductor and the gate insulating film upon application of voltage is represented by: EQU .epsilon.iEi=.epsilon.sEs (1)
where .epsilon.i, .epsilon.s are dielectric constants of the gate insulating film and semiconductor, respectively, and Ei, Es are electric field strengths of the gate insulating film and semiconductor, respectively. Accordingly, the electric field of the gate insulating film is represented by the following equation: ##EQU1## Since .epsilon.S of Si is 11.7 and .epsilon.i of the SiO.sub.2 film is 3.8, an electric field that is about 3 times as much as that of Si substrate is applied to the gate insulating film even in the case where a breakdown electric field is applied to the Si substrate. This electric field is equivalent to about 30% of the breakdown electric field of the gate insulating film. On the other hand, the .epsilon.S of SiC is 10.2, which is not so different from that of Si, but its breakdown electric field is larger than that of Si by about one order of magnitude, as mentioned above. In the SiC device, therefore, an electric field that is ten times as high as that in the case of the Si device is applied to the gate insulating film.
Furthermore, the trench structure as shown in FIG. 10 includes corner portions 15a. The presence of the corner portions 15a prevents the SiC device from taking advantage of its high breakdown electric field since an electric field is concentrated at this corner portion. Namely, as voltage applied to the device is increased, the gate insulating film reaches its breakdown electric field before the semiconductor reaches its breakdown electric field, thus causing the device to break down.
Recently, Shenoy, J. N. et al. has reported in 54.sup.th Device Research Conference, Santa Barbara (1996) on a prototype of SiC vertical MOSFET having a high withstand voltage. FIG. 11 is a cross sectional view showing a part of the SiC vertical MOSFET. The report states that this semiconductor device is produced by double ion implantation, though no description is provided on details of the manufacturing method. In FIG. 11, p base region 23 and n source region 24 are formed by applying increased acceleration voltage upon ion implantation so as to introduce respective impurities to large depth, thereby solving the problem of diffusion of impurities as mentioned above. This SiC vertical MOSFET is in the form of a planar structure, and is therefore free from the above-described problem of the withstand voltage of the oxide film in the trench structure.
The double ion implantation method as described above, however, has the following problem. Namely, ion implantation (or the degree of introduction of ions) varies to a great extent in different directions, whereas diffusion of impurities occurs substantially in the same way in all directions. If ions are implanted in a selected region of the substrate using a mask, therefore, the amount of impurities introduced sideways from the edge of the mask is reduced. Namely, in FIG. 11, the lateral dimension of the p base region 23, i.e., the length of the channel region 30, is reduced relative to the thickness of the region 23 in the depth direction. With the length of the channel region 30 thus reduced, punch-through is more likely to occur, and the withstand voltage cannot be increased.